A wide variety of memory devices can be used to maintain and store data and instructions for various computers and similar systems. In particular, flash memory is a type of electronic memory media that can be rewritten and that can retain content without consumption of power. Unlike dynamic random access memory (DRAM) devices and static random memory (SRAM) devices in which a single byte can be erased, flash memory devices are typically erased in fixed multi-bit blocks or sectors. Flash memory technology can include NOR flash and NAND flash, for example. NOR flash evolved from electrically erasable read only memory (EEPROM) chip technology, in which, unlike flash, a single byte can be erased; and NAND flash evolved from DRAM technology. Flash memory devices are less expensive and denser as compared to many other memory devices, meaning that flash memory devices can store more data per unit area.
Flash memory devices can include a number of sectors that can include word lines and bit lines associated with memory cells to or from which data can be written and/or read. Each sector can include a plurality of memory cells. Further, each sector can include a boost-strap node to which a voltage can be applied in order to facilitate writing or reading data to/from the flash memory. During a read operation, a voltage source can supply a voltage, so that the respective voltage levels at the boost-strap nodes respectively associated with each of the sectors can be increased to a desired voltage level. The boost-strap node can facilitate enabling the signal at the vertical word line to pass to the memory cell word line to facilitate the reading of data from the memory cell associated with the memory cell word line. The desirable amount of time to raise the boost-strap node voltage to the desired voltage level can be limited. Further, parasitic elements can delay the increase of the voltage level in the boost-strap nodes and/or introduce inconsistencies between the voltage ramp rates of the boost-strap nodes of respective sectors, where such parasitic elements can include resistance in the channel associated with the boost-strap nodes as well as stray capacitance, which can result from the routing of the circuitry in the device.
As flash memory devices have continued to evolve, the density of data stored in such devices has increased. To accommodate the increased data, routing channels in flash memory devices can be made more narrow, which can result in an increase in parasitic resistance in the channel, especially over longer distances in the channel, and flash memory devices also have been subject to more compact routing, which can result in an increase in stray capacitance. As a result, there can be undesirable inconsistency in the boost-strap node ramp rate.
Typically, in a flash memory device, there can be a voltage source and a number of boost-strap nodes, where each boost-strap node can be associated with a sector. Each succeeding sector, and thus, each succeeding boost-strap node, can be situated further away from a preceding sector and associated boost-strap node as well as further away from the voltage source (e.g., booster source) that can be associated with the boost-strap node. During a read operation, the time allowed for boost-strap node to settle at a desired voltage can be very limited. As a result, boost-strap node(s) that are situated far away from the source may not be able to settle and reach the target voltage level, due at least in part to the parasitic resistance and capacitance in the routing channel. This can affect the vertical word line and can prevent the vertical word line from passing to the memory cell word line. It is desirable to maintain a consistent boost-strap node ramp rate and ensure that vertical word lines are passed to the memory cell word lines. Further, it is desirable to increase the speed of read operations.